The present invention relates, in general, to chemical mechanical planarization (CMP) systems, and more particularly, a carrier assembly used in CMP systems.
Chemical mechanical planarization (also referred to as chemical mechanical polishing) is a proven process in the manufacture of advanced integrated circuits. CMP is used in almost all stages of semiconductor device fabrication. Chemical mechanical planarization allows the creation of finer structures via local planarization and for global wafer planarization to produce high density vias and interconnect layers. Materials that undergo CMP in an integrated circuit manufacturing process include single and polycrystalline silicon, oxides, nitrides, polyimides, aluminum, tungsten, and copper.
At this time, the expense of chemical mechanical planarization is justified for components such as microprocessors, ASICs (application specific integrated circuits), and other semi-custom integrated circuits that have a high average selling price. The main area of use is in the formation of high density multi-layer interconnects required in these types of integrated circuits. Commodity devices such as memories use little or no CMP because of cost.
The successful implementation of chemical mechanical planarization processes for high volume integrated circuit designs illustrates that major semiconductor manufacturers are embracing this technology. Semiconductor manufacturers are driving the evolution of CMP in several areas. A first area is cost, as mentioned hereinabove, CMP processes are not used in the manufacture of commodity integrated circuits where any increase in the cost of manufacture could impact profitability. Much of the research in CMP is in the area of lowering the cost per wafer of a CMP process. Significant progress in the cost reduction of CMP would increase its viability for the manufacture of lower profit margin integrated circuits. A second area is a reduction in the size or footprint of CMP equipment. A smaller footprint contributes to a reduced cost of ownership. Current designs for chemical mechanical planarization tools take up a significant amount of floor space in semiconductor process facility.
A third area being emphasized is manufacturing throughput and reliability. CMP tool manufacturers are focused on developing machines that can planarize more wafers in less time. Increased throughput is only significant if the CMP tool reliability also increases. A fourth area of study is the removal mechanism of semiconductor materials. Semiconductor companies are somewhat reliant on a limited number of chemical suppliers for the slurries or polishing chemistries used in different removal processes. Some of the slurries were not developed for the semiconductor industry, but came from other areas such as the glass polishing industry. Research will inevitably lead to high performance slurries that are tailored for specific semiconductor wafer processes. Advances in slurry composition directly impact removal rate, particle counts, selectivity, and particle aggregate size. A final area of research is post CMP processes. For example, post CMP cleaning, integration, and metrology are areas where tool manufacturers are beginning to provide specific tools for a CMP process.
Accordingly, it would be advantageous to have a chemical mechanical planarization tool that has improved reliability in a manufacturing environment. It would be of further advantage for the chemical mechanical planarization tool to reduce the cost of polishing each wafer.